Create a vector that specifies the positions of the bits to get.

bit = [1,2,5,7,4]

bit = 1×5
1 2 5 7 4

Get the binary representation of the bits of a at the positions specified in bit.

c = bitget(a,bit)

c =
0 0 1 0 0
DataTypeMode: Fixed-point: binary point scaling
Signedness: Unsigned
WordLength: 1
FractionLength: 0

bitget returns a vector of the bits of a at the positions specified in bit. The output vector has the same length as inputs, a and bit, and a word length of 1.

Get Bit When Input Is Scalar and Index Is a Vector

Input array, specified as a scalar, vector, matrix, or multidimensional
array of fixed-point fi objects. If a and bit are
both nonscalar, they must have the same dimension. If a has
a signed numerictype, the bit representation of
the stored integer is in two's complement representation.

Data Types: fixed-point fi

bit — Bit index scalar | vector | matrix | multidimensional array

Bit index, specified as a scalar, vector, matrix or multidimensional
array of fi objects or built-in data types. If a and bit are
both nonscalar, they must have the same dimension. bit must
contain integer values between 1 and the word length
of a, inclusive. The LSB (right-most
bit) is specified by bit index 1 and the MSB (left-most
bit) is specified by the word length of a. bit does
not need to be a vector of sequential bit positions; it can also be
a variable index value.

Output array, specified as an unsigned scalar, vector, matrix,
or multidimensional array with WordLength 1.

If a is an array and bit is
a scalar, c is an unsigned array with word length
1. This unsigned array comprises the values of the bits at position bit in
each fixed-point element in a.

If a is a scalar and bit is
an array, c is an unsigned array with word length
1. This unsigned array comprises the values of the bits in a at
the positions specified in bit.

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

For VHDL^{®}, generates the slice operator: a(idx).

For Verilog^{®}, generates the slice operator: a[idx].

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